With an aim of utilizing energy at high efficiency, conversion of a material from Si (silicon) to SiC (silicon carbide) has now been under consideration for power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). This is because SiC is a semiconductor having an dielectric breakdown field strength about seven times and a forbidden band gap about three times as much as those of Si, and is suitable to power MOSFETs capable of operation with less loss and at high temperature.
In recent years, development of SiC MOSFETs has been progressed and a low on-resistance below 10 mΩcm2 at a 600 to 1200 V withstanding voltage is obtained. This is sufficiently low compared with that of Si IGBT (Insulated Gate Bipolar Transistor) or Si super junction MOSFET at an identical withstanding voltage. However, in view of intrinsic characteristics to be obtained from the SiC semiconductor, the on-resistance can be further decreased.
One of the subjects concerning the on-resistance of the SiC MOSFET is high channel resistance inherent to SiC. Generally, crystals of 4H—SiC having a Si face on the surface are used for a substrate. In a DMOSFET (Double-Diffused MOSFET) using the Si face as a channel and forming a gate insulating film by dry oxidation or wet oxidation, the mobility is 10 cm2/Vs or less (for example, refer to T. Kimoto et al., “Interface Properties of Metal-Oxide-Semiconductor Structures on 4H—SiC {0001} and (11-20) Formed by N2O Oxidation”, Japanese Journal of Applied Physics, Vol. 44, pp. 1213-1218, 2005). This is because the interface state between a SiC substrate and a gate insulating film is from 1012 to 1013 cm−2 eV−1 which is higher by two digits or more than Si. The low mobility increases the channel resistance and, as a result, hinders decrease in the on-resistance.
Generally, it has been known that JFET (Junction FET) resistance or accumulation resistance can be decreased by changing the device structure from a DMOSFET to a trench MOSFET and the mobility can be improved further in SiC by utilizing the A face as a face vertical to the Si face as a channel (for example, refer to T. Kimoto et al., “Interface Properties of Metal-Oxide-Semiconductor Structures on 4H—SiC {0001} and (11-20) Formed by N2O Oxidation”, described above. In this case, a mobility of 50 cm2/Vs or more can be expected. Accordingly, by adopting the trench MOSFET for the SiC semiconductor, the mobility is improved and the channel resistance can be decreased.
Further, since the channel can be vertical to the substrate in the trench MOSFET, this is advantageous in view of, the integration degree compared with the DMOSFET where the channel is horizontal to the substrate and, as a result, it can be expected that the channel resistance is decreased further.
A manufacturing method disclosed in Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2004-522319 has been known as a method of manufacturing a trench MOSFET in the Si semiconductor. In this method, a silicide for obtaining a good low resistance contact with a source electrode is formed in a source region after forming a dielectric layer (gate insulating film) to the wall of the trench.
Further, a manufacturing method disclosed in Japanese Unexamined Patent Application Publication No. 2006-261624 has been known as a method of manufacturing a silicon carbide device. In this method, for suppressing a thermal load on the semiconductor-gate oxide film interface in a high temperature treatment accompanying ion implantation or annealing for connection metal, a silicide is formed before forming the gate insulating film.